The present disclosure relates to a semiconductor memory device and, more particularly, to a semiconductor memory device using a high voltage.
A flash memory device is a non-volatile memory device that requires no power to retain information stored therein. Further, although a flash memory device does not operate at a higher speed than a DRAM used as a main memory in a PC, its read speed is high and is strong against impact compared to a hard disk.
A flash memory device is widely used as storage in applications that are powered by a battery. Further, a flash memory device is strong and able to endure high pressure and hot water.
A flash memory device is a computer memory device that is capable of electrically erasing and rewriting data. Unlike EEPROM, a flash memory device operates an erase/write operation in a block unit. A flash memory device is widely used in applications that require large-volume, non-volatile, and solid-state storage because it is less costly than EEPROM. The applications may include MP3 players, digital cameras, mobile phones, and the like. USB drives have been used to store data and to move data between computers. Conventional USB devices use flash memory devices.
A flash memory device with a split gate structure is used to store BIOS startup information for a personal computer or to store programs or data files for portable equipment such as mobile telephones and digital cameras, for example
FIG. 1 is a cross-sectional view of a flash memory device with a split gate, and FIG. 2 is a schematic illustration of a flash memory cell which is an equivalent circuit of the split-gate flash memory device of FIG. 1.
Referring to FIG. 1, the split-gate flash memory device 100 includes a source region 102, a drain region 103 formed on a semiconductor substrate 101 and spaced apart from the source region 102 by the length of a channel region 104, a floating gate 105 formed over predetermined portions of the source region 102 and the channel region 104, and a control gate 106 formed over both the floating gate 105 and the channel region 104, and disposed at a lateral portion of the floating gate 105. The split-gate flash memory device 100 performs a program operation by accumulating a negative charge in the floating gate 105, and performs an erase operation by tunneling the accumulated charge to the control gate 106 at a peak portion A of the floating gate 105.
Referring to FIG. 2, the flash memory cell 200 includes a memory transistor 201 and a select transistor 202 that are serially connected between a source line SL and a bit line BL and are gated in common to a word line WL. The program or erase operation of the flash memory cell 200 may be achieved under the conditions of TABLE 1.
TABLE 1OperationSel/UnselBLWLSLBULKProgramSel0 V1.5 V10 V0 VUnselVCC  0 V 0 V0 VEraseSel0 V 12 V 0 V0 VUnsel0 V  0 V 0 V0 VReadSel1 V  3 V 0 V0 VUnsel0 V  0 V 0 V0 V
Voltages illustrated in TABLE 1 are exemplary, and may be changed appropriately for various flash memory devices.
As shown in TABLE 1, when applying 0V to the bit line BL, 1.5V (a threshold voltage VT of a transistor) to the word line WL, 10V (high voltage Vpp) to the source line SL and a bulk voltage of 0V, charge is accumulated in the floating gate 105 of the memory transistor 201 to thereby achieve the program operation of the flash memory cell 200.
When applying 0V to the bit line BL, 12V (erase voltage) to the word line WL, 0V to the source line SL and a bulk voltage of 0V, the accumulated charge of the floating gate 105 is discharged to thereby achieve the erase operation of the flash memory cell 200.
The read operation of the flash memory cell 200 is achieved by applying IV to the bit line BL, 3V (read voltage) to the word line WL, 0V to the source line SL and a bulk voltage of 0V. At this time, when a selected memory cell is a programmed cell, current does not flow between the drain and the source of the memory transistor 201, and thus, the memory cell is referred to as being “off”. Meanwhile, if a selected cell is an erased cell, constant current flows between the drain and the source of the memory transistor 201, and thus, the memory cell is referred to as being “on”.
A high voltage applied to a source line SL of a memory cell 200 may be maintained constant to increase the efficiency of the Hot Carrier Injection (HCI) for accumulating negative charge in a floating gate 105 of the flash memory device 100 of FIG. 1.
A high voltage from a high voltage generator circuit in a flash memory device may be applied to a source line via a source line decoder circuit. The source line decoder circuit may include one or more transistors for driving the source line, whose threshold voltages are varied according to a peripheral temperature. Accordingly, a program operation is affected by variation of the high voltage applied to a source line of a memory cell.